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ADE7518
Table 21. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit
7 to 0
Mnemonic
SCRATCH2
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 22. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit
7 to 0
Mnemonic
SCRATCH3
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit
7 to 0
Mnemonic
SCRATCH4
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Clearing the Scratch Pad Registers (SCRATCH1, 0xFB to SCRATCH4, 0xFE)
Note that these scratch pad registers are only cleared when the part loses V DD and V BAT . They are not cleared by software, watchdog, or
PLL reset and, therefore, need to be set correctly in these situations.
Table 24. Power Control SFR (POWCON, 0xC5)
Bit
7
6
Mnemonic
Reserved
METER_OFF
Default
1
0
Description
Reserved.
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if
metering functions are not needed in PSM0.
5
4
3
2 to 0
Reserved
COREOFF
Reserved
CD[2:0]
0
0
0
010
This bit should be kept at 0 for proper operation.
Set this bit to shut down the core and enter PSM2 if in PSM1 operating mode.
Reserved.
Controls the core clock frequency, f CORE . f CORE = 4.096 MHz/2 CD .
CD[2:0] Result (f CORE in MHz)
000 4.096
001 2.048
010 1.024
011 0.512
100 0.256
101 0.128
110 0.064
111 0.032
Writing to the Power Control SFR (POWCON, 0xC5)
Writing data to the POWCON SFR involves writing 0xA7 into the Key SFR (KYREG, 0xC1), which is described in Table 105, followed by
a write to the POWCON SFR. For example,
MOV KYREG,#0A7h
MOV POWCON,#10h
;Write KYREG to 0xA7 to get write access to the POWCON SFR
;Shutdown the core
Rev. 0 | Page 24 of 128
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